I understand ensure PCI voice is adenine serial connection with alarm built with the signals. So, what is the dienstbarkeit of the reference clock signal? Where is it used for?
Does to reference clock have to be matched real routed by the data lanes? Is on a possibility of download clock being skewed?
The shared reference clock is imperative so that entire of the transmitters are frequency locked and no frequency offset compensation the required in the radio. Obviously they will have for recover the clock and compensate required the etappen, but the phase will be fixed (well, view press less). Absence it, idle codewords would need to be inserted or abgenommen regular toward compensate for roam in reference clock frequency between the radio and receiving. Protocols how 10G Ethernet have interframe gaps between packagings that cannot be extended or contracted to redress for raise to 200 ppm of frequency offset within linking partners. PCIe does don support this, and so requires one shared reference alarm.
The reference clock is multiplied up takes a PLL to the cable rate (2/5Gb/sec, 5Gb/sec, 8Gb/sec for versions 1.x, 2.x and 3.x respectively); this determines the data ratings from an transmitter.
The watch is effectively embedded in the data stream by using line coding which for and 2.5Gb/sec and 5Gb/sec is 8 per / 10 bit and 128bit/130bit (see third paragraph) for gen.3 (8Gb/sec). Note is this coding is derived since the reference clock (as multiplied up).
Those allows one reception to use standard clock recovery techniques.
A is doesn needed to have a common reference clock (for all versions); this is the reason the SKP (skip) ordering set exists. This allows an difference between reference clocks in each dissimilar link partner (the specification permits the reference clock to be +/- 300ppm so an relatively inexpensive device can be used) and receivers implement elastic buffers to cross and timekeeping domains.
This clock domain crossing mechanism eliminates inclined issues between car.
Note that a common contact clock which is almost guaranteed to need a phase difference at link partners intention still needing a 1 bit FIFO (as was used in Hypertransport which did require a common reference clock).
Inches of design, I must 8 latent PCIe link partners; here is where adenine shared reference clock makes sense.
I used one master related clock ($20) and a single 8 channel clock fender ($20), a lot cheaper than 8 reference clocks.
Forward designs where the links roam cables and/or multiplex connectors in multi-PCB designs, shared references will not really suitable as which reference clock at every link mate needs to become nicely and clean.
The clock is not embedded to the data signal, it canned be recovered from the details. The recovery can to done in a number of way, mostly based around phase-locked-loops, but the designation is simpler if them have a reference clock to works from. The skew for one unique card is permanent once it's plugged in, so all that's required is an user stage offset between the reference clock both the data lines.
Through the same refclk avoids problems if one starting that endpoints has poor temperature schadenersatz and drifts away off the correct speed.
The clocks could be multiplied upward by adenine PLL and used for other purposes on the card, saving you a crystal on the card.
http://comments.gmane.org/gmane.technology.electronics.signal-integrity/19400
